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19-1702; Rev 0; 4/00
2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater
General Description
The MAX3752/MAX3753 quad-port bypass ICs are designed for use in the Fibre Channel Arbitrated Loop topology. These devices consist of four serially connected port bypass circuits (PBCs) and a repeater that provides clock and data recovery (CDR). The quad-port bypass circuit allows connection of up to four Fibre Channel L-Ports, which can each be enabled or bypassed by controlling the PBC select inputs. Additional quad PBCs can be cascaded for applications requiring more than four L-Ports. To reduce the external parts count, all signal inputs and outputs have internal termination resistors. The MAX3752/MAX3753 comply with Fibre Channel jitter tolerance requirements and can recover data signals with up to 0.7 unit intervals (UIs) of high-frequency jitter. When the repeater is not needed, it can be disabled to reduce power consumption. A fully integrated phaselocked loop (PLL) provides a frequency lock indication and does not need an external reference clock. Two pin-compatible versions of the quad PBC are available--the MAX3752 for 2.125Gbps or 1.063Gbps operation, and the MAX3753 for 1.063Gbps operation. o Four High-Speed Data Ports o Meets Fibre Channel Jitter Tolerance Requirements o Large Output Signal Swing (>1000mVp-p) o +3.0V to +3.6V Single-Supply Voltage o On-Chip Termination Resistors Compatible with 75 Transmission Lines at All Ports
Features
MAX3752/MAX3753
Ordering Information
PART MAX3752CCM MAX3753CCM** TEMP. RANGE 0C to +70C 0C to +70C PIN-PACKAGE 48-pin TQFP-EP* 48-pin TQFP-EP*
*EP = Exposed pad **Future product--contact factory for availability.
________________________Applications
2.125Gbps Fibre Channel 1.063Gbps Fibre Channel
LOUT2+ LOUT2GND LIN2+ LIN2-
Pin Configuration
LOUT3+ LOUT3GND
41 40 39
Storage Area Networks Fibre Channel Hubs
GND LIN1LIN1+ GND LOUT1LOUT1+ GND GND ININ+ GND CLKEN
1 2 3 4 5 6 7 8 9 10 11 12
48
47
46
45
44
43
42
38
37
LIN3+ LIN3-
Fibre Channel Data Storage Systems
GND GND
36 35 34 33 32 31
Typical Operating Circuit appears at end of data sheet.
MAX3752/MAX3753
30 29 28 27 26 25
GND LOUT4+ LOUT4GND LIN4+ LIN4GND GND OUTOUT+ GND LOCK
13
14
15
16
17
18
19
20
21
22
23
VCC SEL1 SEL2
SEL3 SEL4 VCC
VCC
CFP CFM
CDREN LOCKEN
TQFP-EP* * Exposed pad is connected to ground. ________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
VCC
24
2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +5.0V Current into OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-, LOUT3+, LOUT3-, LOUT4+, LOUT4- ......................0 to 22mA Voltage at OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-, LOUT3+, LOUT3-, LOUT4+, LOUT4-....................................... .......................................................(VCC - 1.65V) to (VCC + 0.5V) Voltage at IN+, IN-, LIN1+, LIN1-, LIN2+, LIN2-,LIN3+, LIN3-, LIN4+, LIN4-. ..........................................-0.5V to (VCC + 0.5V) Voltage at CLKEN, CFP, CFM, SEL1, SEL2, SEL3, SEL4, CDREN, LOCKEN.......................................-0.5V to (VCC + 0.5V) Voltage at LOCK.........................................-0.5V to (VCC + 0.5V) Current at LOCK .................................................-10mA to +1mA Continuous Power Dissipation (TA = +70C) TQFP-EP (derate 27.0mW/C above +70C) ......................2W Operating Junction Temperature Range ...........-55C to +150C Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-50C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +70C. Typical values are at +3.3V, CLKEN = LOW, LOCKEN = LOW, TA = +25C, unless otherwise noted.)
PARAMETER CDR disabled (CDREN = GND) Supply Current (Note 1) CDR enabled (CDREN = Vcc) Input Swing (Differential) Input Common-Mode Voltage Output Voltage Swing (Differential) 150 load (OUT, LOUTn) Input Resistance (Differential) Output Resistance (Differential) TTL Input Voltage (Low) TTL Input Voltage (High) TTL Input Current Lock Output Voltage (Low) Lock Output Voltage (High) Voltage at CFP, CFM 0 TTL input voltage VCC IOL = +1mA, LOCKEN = HIGH IOH = -100A, LOCKEN = HIGH 2.4 2 -50 0.4 VCC 0.4 VCC 1.03 50 0.7 (IN, LINn) (OUT, LOUTn) 1000 132 132 IN, LINn CONDITIONS MAX3753 MAX3752 MAX3753 MAX3752 198 200 VCC 0.45 1400 150 150 1600 181 181 0.8 151 MIN TYP 195 193 225 255 353 2200 mVp-p V mVp-p V V A V V V 269 mA MAX UNITS
2
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater
AC ELECTRICAL CHARACTERISTICS--MAX3752 Operating at 2.125Gbps
(VCC = +3.0V to +3.6V, TA = 0C to +70C. Typical values are at +3.3V, CF = 0.22F, TA = +25C, unless otherwise noted.) (Notes 2-7)
PARAMETER Data Rate Output Edge Speed Random Jitter at OUT 20% to 80% Pattern = K28.7+, CDR disabled Pattern = K28.7+, CDR enabled Pattern = CRPAT, CDR enabled (Note 8) Pattern = K28.5, CDR disabled Deterministic Jitter at OUT Pattern = K28.5, CDR enabled Pattern = FC-RPAT, CDR enabled (Note 8, jitter applied) Total Jitter at OUT Jitter Tolerance (BER = 10-12) Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance CDR Lock Time BER = 10-12 (Note 10) Pattern = CJTPAT IN to OUT (ports bypassed, CDR enabled) LINn to LOUT(n+1) (port normal mode) Propagation Delay SEL(n) rising edge to data valid at LOUT(n+1) or OUT (port normal mode) SEL(n) falling edge to data valid at LOUT(n+1) or OUT (port bypass mode) 8 8 Pattern = CRPAT, CDR enabled Pattern = CRPAT, CDR enabled (Note 8, jitter applied) f = 85kHz sine wave (Notes 8, 9) f = 1.27MHz sine wave (Notes 8, 9) f = 10MHz sine wave (Notes 8, 9) 1.5 0.1 0.1 0.38 0.7 4.4 10 2 ns CONDITIONS MIN 75 TYP 115 1.5 2.3 3.6 39 27 52 72 100 >4.22 >0.85 >0.47 UIp-p UIp-p ms UIp-p 82 47 80 psp-p psp-p psRMS MAX 160 UNITS Gbps ps
MAX3752/MAX3753
2.125 100ppm
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
AC ELECTRICAL CHARACTERISTICS--MAX3752 Operating at 1.063Gbps
(VCC = +3.0V to +3.6V, TA = 0C to +70C. Typical values are at +3.3V, CF = 0.22F, TA = +25C, unless otherwise noted.) (Notes 2-7)
PARAMETER Data Rate Output Edge Speed Random Jitter at OUT 20% to 80% Pattern = K28.7+, CDR disabled Pattern = K28.7+, CDR enabled Pattern = CRPAT, CDR enabled (Note 8) Pattern = K28.5, CDR disabled Deterministic Jitter at OUT Pattern = K28.5, CDR enabled Pattern = FC-RPAT, CDR enabled (Note 8, jitter applied) Total Jitter at OUT Jitter Tolerance (BER = 10-12) Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance CDR Lock Time BER = 10-12 (Note 10) Pattern = CJTPAT IN to OUT (ports bypassed, CDR enabled) LINn to LOUT(n+1) (port normal mode) Propagation Delay SEL(n) rising edge to data valid at LOUT(n+1) or OUT (port normal mode) SEL(n) falling edge to data valid at LOUT(n+1) or OUT (port bypass mode) 8 8 Pattern = CRPAT, CDR enabled Pattern = CRPAT, CDR enabled (Note 8, jitter applied) f = 42.7kHz sine wave (Notes 8, 9) f = 637MHz sine wave (Notes 8, 9) f = 5MHz sine wave (Notes 8, 9) 1.5 0.1 0.1 0.19 0.35 4.4 10 2 ns CONDITIONS MIN 75 TYP 115 1.5 2.3 4.2 39 27 58 59 116 >2.81 >0.5 >0.22 UIp-p UIp-p ms UIp-p 82 47 110 psp-p psp-p psRMS MAX 160 UNITS Gbps ps 1.063 100ppm
4
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater
AC ELECTRICAL CHARACTERISTICS--MAX3753 Operating at 1.063Gbps
(VCC = +3.0V to +3.6V, TA = 0C to +70C. Typical values are at +3.3V, CF = 0.22F, TA = +25C, unless otherwise noted.) (Notes 2-7)
PARAMETER Data Rate Output Edge Speed Random Jitter at OUT 20% to 80% Pattern = K28.7+, CDR disabled Pattern = K28.7+, CDR enabled Pattern = CRPAT, CDR enabled (Note 8) Pattern = K28.5, CDR disabled Deterministic Jitter at OUT Pattern = K28.5, CDR enabled Pattern = FC-RPAT, CDR enabled (Note 8, jitter applied) Total Jitter at OUT Jitter Tolerance (BER = 10-12) Deterministic Jitter Tolerance Total High-Frequency Jitter Tolerance CDR Lock Time BER = 10-12 (Note 10) Pattern = CJTPAT IN to OUT (ports bypassed, CDR enabled) LINn to LOUT(n+1) (port normal mode) Propagation Delay SEL(n) rising edge to data valid at LOUT(n+1) or OUT (port normal mode) SEL(n) falling edge to data valid at LOUT(n+1) or OUT (port bypass mode) Pattern = CRPAT, CDR enabled Pattern = CRPAT, CDR enabled (Note 8, jitter applied) f = 42.5kHz sine wave (Notes 8, 9) f = 637MHz sine wave (Notes 8, 9) f = 5MHz sine wave (Notes 8, 9) 1.5 0.1 0.1 0.38 0.7 4.4 2 1 8 8 ns CONDITIONS MIN TYP 215 1.5 2.3 3.6 39 27 52 72 100 >4.22 >0.85 >0.47 UIp-p UIp-p ms UIp-p psp-p psp-p psRMS MAX UNITS Gbps ps
MAX3752/MAX3753
1.063 100ppm
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
AC ELECTRICAL CHARACTERISTICS--MAX3753 Operating at 1.063Gbps (continued)
Note 1: Includes output currents. Note 2: AC characteristics are guaranteed by design and characterization. Note 3: K28.7+ Pattern: 0011 1110 00. Note 4: Fibre Channel Random Pattern in hex (FC-RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65. Note 5: Compliant Random Pattern in hex (CRPAT): Pattern Sequence Repetitions 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65 16 72 31 9A 95 AB 1 C1 6A AA 9A A6 1 Note 6: K28.5 Pattern: 0011 1110 1011 0000 0101. Note 7: Compliant Jitter Tolerance Pattern in Hex (CJTPAT): Pattern Sequence Repetitions 3E AA 2A AA AA 6 3E AA A6 A5 A9 1 87 1E 38 71 E3 41 87 1E 38 70 BC 78 F4 AA AA AA 1 AA AA AA AA AA 12 AA A1 55 55 E3 87 1E 38 71 E1 1 AB 9C 96 86 E6 1 C1 6A AA 9A A6 1 Note 8: Parameter measured with 0.38UI deterministic and 0.22UI random jitter (BER = 10-12) applied to the input. Note 9: Jitter tolerance measurement exceeds the capability of the test equipment used. Note 10: Parameter measured with 0.1UI sinusoidal jitter at 10MHz plus 0.38UI deterministic jitter applied to the input.
Typical Operating Characteristics
(TA = +25C and VCC = +3.3V, unless otherwise noted.)
MAX3752 SUPPLY CURRENT vs. TEMPERATURE
275 SUPPLY CURRENT (mA) 250 225 200 175 150 125 100 0 10 20 30 40 50 60 70 200ps/div 100ps/div TEMPERATURE (C) REPEATER DISABLED 100mV/div 100mV/div
MAX3752/3-01
MAX3752 DATA OUTPUT EYE DIAGRAM (1.0625Gbps CJTPAT)
MAX3752/3-02
MAX3752 DATA OUTPUT EYE DIAGRAM (2.125Gbps CJTPAT)
MAX3752/3-03
300 REPEATER ENABLED
6
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
Typical Operating Characteristics (continued)
(TA = +25C and VCC = +3.3V, unless otherwise noted.)
MAX3752 OUTPUT JITTER--BATHTUB PLOT
MAX3752/3-04
MAX3752 OUTPUT JITTER--BATHTUB PLOT
2Gbps CRPAT (0.38UI DJ, 0.63UI TJ ON INPUTS)
MAX3752/3-05
1.00E+00 1.00E+02 1.00E+04 BIT ERROR RATE
2Gbps CRPAT (NO JITTER ON INPUTS)
1.00E+00 1.00E+02 1.00E+04 BIT ERROR RATE 1.00E+06 1.00E+08 1.00E+10 1.00E+12 1.00E+14
1.00E+06 1.00E+08 1.00E+10 1.00E+12 1.00E+14 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DATA SAMPLING TIME RELATIVE TO FIRST ZERO CROSSING (UI)
MAX3752 INPUT VSWR vs. FREQUENCY (BY SIMULATION)
MAX3752/3-06
MAX3752 OUTPUT VSWR vs. FREQUENCY (BY SIMULATION)
MAX3752/3-07
4
4
3 VSWR VSWR 2
3
2
1 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 FREQUENCY (GHz)
1 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 FREQUENCY (GHz)
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
Pin Description
PIN 1, 4, 7, 8, 11, 26, 29, 30, 33, 36, 39, 42, 43, 46 2 3 5 6 9 10 12 13,16, 21, 24 14 15 17 18 19 20 22 23 25 27 28 31 32 34 35 37 38 40 41 44 45 47 48 EP NAME GND LIN1LIN1+ LOUT1LOUT1+ ININ+ CLKEN VCC CFP CFM SEL1 SEL2 SEL3 SEL4 CDREN LOCKEN LOCK OUT+ OUTLIN4LIN4+ LOUT4LOUT4+ LIN3LIN3+ LOUT3LOUT3+ LIN2LIN2+ LOUT2LOUT2+ Exposed Pad Electrical Ground Inverted Data Input for L-Port 1 Noninverted Data Input for L-Port 1 Inverted Data Output for L-Port 1 Noninverted Data Output for L-Port 1 Inverted Data Input Noninverted Data Input Clock Enable. A TTL high level enables clock output at L-Port 1. Positive Supply Voltage CDR Filter Capacitor Positive Connection CDR Filter Capacitor Negative Connection Select 1. A TTL low on SEL1 selects data from IN. TTL high on SEL1 selects data from LIN1. Select 2. A TTL low on SEL2 selects data from the previous port bypass circuit. A TTL high on SEL2 selects data from LIN2. Select 3. A TTL low on SEL3 selects data from the previous port bypass circuit. A TTL high on SEL3 selects data from LIN3. Select 4. A TTL low on SEL4 selects data from the previous port bypass circuit. A TTL high on SEL4 selects data from LIN4. CDR Enable Input (TTL). A high input enables the CDR for data recovery. A low input disables the CDR (no data recovery). Lock Enable Input (TTL). A high input enables the LOCK output. A low input disables the LOCK output. CDR Lock Output. Enabled by LOCKEN. A high output indicates the CDR PLL is locked. When LOCKEN is low, LOCK is high. Noninverted Data Output Inverted Data Output Inverted Data Input for L-Port 4 Noninverted Data Input for L-Port 4 Inverted Data Output for L-Port 4 Noninverted Data Output for L-Port 4 Inverted Data Input for L-Port 3 Noninverted Data Input for L-Port 3 Inverted Data Output for L-Port 3 Noninverted Data Output for L-Port 3 Inverted Data Input for L-Port 2 Noninverted Data Input for L-Port 2 Inverted Data Output for L-Port 2 Noninverted Data Output for L-Port 2 Ground. The exposed pad must be soldered to the circuit board for proper thermal performance. FUNCTION
8
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
LOUT1+ LOUT2+ LOUT3+ LOUT4+ LOUT1LOUT2LOUT3LOUT4LIN1+ LIN2+ LIN3+ LIN1LIN2LIN3LIN4CF CFP CFM CLKEN LIN4+
TTLIN LOCK LOCKEN
CDR DIN DOUT
CLK EN
D1 D0 Q D0 Q D1 D0 Q D1 D0 Q D1 D0 Q D1 VCC GND TTLIN TTLIN TTLIN TTLIN OUT+ OUT-
IN+ IN-
D0 Q D1
TTLIN
MAX3752 MAX3753
CDREN
SEL1
SEL2
SEL3
SEL4
Figure 1. Functional Diagram
Detailed Description
The MAX3752/MAX3753 quad PBCs consist of an input buffer, a clock/data recovery circuit (for optional data recovery), four serially connected port bypass circuits, and an output buffer (Figure 1). The circuit design is optimized for both high-speed (1Gbps to 2Gbps) and low-voltage (+3.3V) operation.
clock signal is available for test purposes at LOUT1 (the output of the first port bypass circuit) when the clock enable input (CLKEN) is set to a TTL high level. A TTL low on CDREN disables the CDR and connects the input buffer output directly to the port bypass circuits.
Port Bypass Circuits
The output of the 2:1 input multiplexer drives a cascaded series of four PBCs. Each PBC consists of a differential output buffer, a differential input buffer, and a 2:1 multiplexer. The multiplexer select input (SELn) controls which multiplexer input is connected to the multiplexer output. A TTL low on the multiplexer select pin causes the data signal from the previous stage to be connected to the multiplexer output (port bypass mode). A TTL high on the multiplexer select pin causes the data signal from the input buffer to be connected to the multiplexer output (port enable mode). The output of the last PBC drives the output buffer.
Input Buffer
The input buffer provides line termination and level conversion. It accepts a differential input voltage of 200mV to 2200mV at the IN+ and IN- pins. Internal resistors terminate each input to 75 (150 total between the two inputs), eliminating the need for external termination resistors in most applications (see Applications Information for a suggested interface to 50 systems).
Clock and Data Recovery
The purpose of the clock and data recovery (CDR) is to improve jitter transfer performance by attenuating jitter that may be present in the input data. The CDR can recover data signals that are corrupted by up to 0.7UI of high-frequency jitter (BER = 10-12). When data recovery is not needed, the CDR may be disabled in order to save power. The input buffer drives the CDR circuit, as well as one input of a 2:1 multiplexer. A TTL high on the CDR enable pin (CDREN) enables the CDR and connects the CDR data output to the port bypass circuits. The recovered
Output Buffer
The output signal of the last PBC drives the differential high-power output buffer. The output buffer drives the output port (OUT). Internal resistors terminate each output to 75 (150 total between the two outputs), eliminating the need for external termination resistors in most applications (see Applications Information for a suggested interface to 50 systems). The output buffer produces a differential output voltage of 1000mV to 1600mV when driving a differential 150 load.
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
PORT BYPASS 0 SERIAL DATA IN MUX 1
PORT BYPASS 0 MUX 1
PORT BYPASS 0 MUX 1
PORT BYPASS 0 MUX 1 SERIAL DATA OUT
IN
OUT L-PORT
SEL
IN
OUT L-PORT
SEL BYPASSED
IN
OUT L-PORT
SEL
DISK DRIVE
DISK DRIVE
DISK DRIVE
Figure 2. Disk Array Implemented with Port Bypass Circuits
Applications Information
The MAX3752/MAX3753 quad-port bypass circuits are designed for hard disk array applications of the Fibre Channel Arbitrated Loop network protocol. A drive array is a collection of hard disk drives (called physical drives) that are connected together. The total storage capacity of the array of physical drives can be divided into one or more subsets (called logical drives) that may be spread over all of the physical drives in the array. For example, a computer accessing the drive array might "see" it as two logical drives (D: and E:, for example) that each have a storage capacity of 20GB, even though the actual array is made up of eight physical 5GB drives. In applications where data storage reliability is critical, it may be desirable to create a disk array where the data is stored redundantly on more than one physical drive. This type of system is generally called a redundant array of inexpensive disks (RAIDs). If a physical drive fails, it may be replaced and the lost data can be restored. Drive arrays are also useful in applications that require fast access to stored data. The data may be distributed over physical drives connected in a parallel arrangement, enabling access to data concurrently from multiple drives in the array. This makes it possible to achieve I/O
10
rates much greater than what is feasible with nonarrayed drives. The Fibre Channel Arbitrated Loop protocol enables multiple physical drives to be connected in a loop topology. Each physical drive is connected to the Fibre Channel loop through an L-Port that may be individually addressed and controlled to create the array of logical drives. Data is transmitted over the loop as an encoded serial bit stream. Using the Fibre Channel Arbitrated Loop protocol, the configuration of the disk array can be rearranged under software control to achieve desired objectives (such as data reliability or fast access). The port bypass circuit allows any L-Port to be enabled (connected to the network) or bypassed (disconnected from the network) while the network is operating. This enables hot swapping of physical drives (inserting or removing physical drives while the network is operating) so that drives may be replaced with minimal disruption to the disk array system. Figure 2 shows the disk array.
Input/Output Structures
Figures 3 and 4 show models for the MAX3752/ MAX3753 inputs and outputs.
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
PACKAGE PARASITICS DIE VCC
ESD STRUCTURES
1k
2.2nH 0.2pF 0.4pF
2.2nH 0.2pF 0.4pF 75 75
VCC - 0.45V
Figure 3. MAX3752/MAX3753 Input Structure
Cascading Port Bypass Circuits
Two or more MAX3752/MAX3753 quad PBCs can be cascaded by directly connecting the OUT+ and OUTpins of one quad PBC to the IN+ and IN- pins of the next quad PBC. See Typical Operating Circuit.
Interfacing to 50 Systems
Figure 5 shows examples of resistive impedance transforming networks that can be used to interface between the 75 input/output structure of the MAX3752/ MAX3753 and 50 systems. The characteristics of the two examples shown can be derived by referring to Figures 3, 4, and 5. The top configuration in Figure 5 is useful in designs where the parallel 300 resistors can be placed very close to the input/output pins of the IC. In this case, the 50 transmission lines should connect directly to the IC. The bottom configuration in Figure 5 provides a better impedance match than the top configuration for designs
where 75 transmission lines are connected between the input/output pins of the IC and the resistive impedance transforming networks. Neither of the two configurations in Figure 5 provides 100% efficient voltage coupling. In the top configuration, the input voltage (VIN) is the same as the source voltage (VSRC), but the output/load voltage (VOUT = VLOAD for this case) is reduced by a factor of 0.67 because the output is loaded with an equivalent of 75. (The data sheet specification for output voltage swing is based on a 150 load.) In the bottom configuration, VIN is attenuated by a factor of 0.64 from VSRC, and VLOAD is attenuated by a factor of 0.43 from VOUT. For example, a source voltage of 625mV will result in an input voltage of 625mV for the top configuration, but only 400mV for the bottom configuration. Also, a typical output voltage swing of 1400mV into a differential 150 load will cause the corresponding load voltage to be
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
VCC DIE PACKAGE PARASITICS ESD STRUCTURES 2.2nH OUT+ 0.4pF 2.2nH OUT0.4pF 0.2pF 0.2pF
940mV for the top configuration and 600mV for the bottom configuration.
Layout Considerations
For best performance, carefully lay out the PC board using high-frequency techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3752/MAX3753 high-speed inputs and outputs. Power-supply decoupling capacitors should be placed very close to VCC pins. Isolate the input signals from the output signals as much as possible.
75
75
19mA
Figure 4. MAX3752/MAX3753 Output Structure
50 Z0 = 50 IN+ OUT+ Z0 = 50
50
+
VSRC
-
300
MAX3752 MAX3753
300
RLOAD = 100
+
VLOAD
-
Z0 = 50 VIN = VSRC
IN-
OUT-
Z0 = 50 VLOAD = 0.67VOUT
50 Z0 = 50
43 Z0 = 75 IN+ OUT+ Z0 = 75
43 Z0 = 50
50
+
VSRC
-
176
MAX3752 MAX3753
43 43 Z0 = 75 VIN = 0.64VSRC INOUTZ0 = 75
176
RLOAD = 100
+
VLOAD
-
Z0 = 50
Z0 = 50 VLOAD = 0.43VOUT
Figure 5. Interfaces to 50 Systems
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater
Typical Operating Circuit
MAX3752/MAX3753
DISK DRIVE L_PORT n IN OUT SEL 2 LOUT1 VCC VCC UPSTREAM L_PORT GND IN+ INCF 0.22F CFP CFM LOUT3 LOUT4 SEL3 LIN3 2 SEL1 LIN1
DISK DRIVE L_PORT n+1 IN OUT SEL 2 LOUT2 2 SEL2 LIN2 VC VCC VCC N.C. Z0 = 75 Z0 = 75 CF 0.22F GND IN+ INCFP CFM LOUT3
DISK DRIVE L_PORT n+4 IN OUT SEL 2 LOUT1 2 SEL1 LIN1
DISK DRIVE L_PORT n+5 IN OUT SEL 2 LOUT2 2 SEL2 LIN2 VCC
CDREN LOCK OUT+
CDREN LOCK OUT+ N.C. DOWNSTREAM L_PORT
MAX3752 MAX3753
OUTCLKEN LOCKEN SEL4 LIN4
MAX3752 MAX3753
OUTCLKEN LOCKEN
LOUT4
SEL3
2
2
2
2
2
2
2
2
IN OUT SEL L_PORT n+2 DISK DRIVE
IN OUT SEL L_PORT n+3 DISK DRIVE
IN OUT SEL L_PORT n+6 DISK DRIVE
IN OUT SEL L_PORT n+7 DISK DRIVE
NOTE: ALL HIGH-SPEED INPUTS AND OUTPUTS (IN, OUT, LIN, AND LOUT) SHOULD BE CONNECTED USING CONTROLLED IMPEDANCE TRANSMISSION LINES. AC-COUPLING MAY ALSO BE REQUIRED. ALL CAPACITORS ARE 0.1F UNLESS OTHERWISE INDICATED.
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SEL4
LIN3
LIN4
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2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
Package Information
14
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48L, TQFP.EPS
2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater
Package Information
MAX3752/MAX3753
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15
2.125Gbps/1.063Gbps, 3.3V Quad-Port Bypass with Repeater MAX3752/MAX3753
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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